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Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
Power-Up Sequence (POR, UVLO)
The MAX17410 is enabled when SHDN is driven high
(Figure 9). The reference powers up first. Once the refer-
ence exceeds its undervoltage lockout threshold, the inter-
nal analog blocks are turned on and masked by a 150μs
one-shot delay. The PWM controller then begins switching.
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch and preparing
the controller for operation. The V CC undervoltage lock-
out (UVLO) circuitry inhibits switching until V CC rises
above 4.25V. The controller powers up the reference
once the system enables the controller, V CC above
4.25V and SHDN driven high. With the reference in reg-
ulation, the controller ramps the output voltage to the
boot voltage (1.2V) at 1/8th the slew rate set by R TIME :
current limit, so full output current is available immedi-
ately. CLKEN is pulled low approximately 60μs after the
MAX17410 reaches the boot voltage. At the same time,
the MAX17410 slews the output to the voltage set at the
VID inputs at the programmed slew rate. PWRGD and
PHASEGD becomes high impedance approximately
5ms after CLKEN is pulled low. The MAX17410 auto-
matically uses forced-PWM operation during soft-start
and soft-shutdown, regardless of the DPRSLPVR and
PSI configuration.
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
t TRAN ( START ) =
8 V BOOT
( dV TARGET / dt )
or cycling the V CC power supply below 0.5V.
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
where dV TARGET /dt = 12.5mV/μs x 71.5k Ω /R TIME is the
slew rate. The soft-start circuitry does not use a variable
V CC
SHDN
voltage faults, the controller shuts down immediately
and forces a high-impedance output.
VID (D0–D6)
SOFT-START =
1/8 SLEW RATE SET BY R TIME
V CORE
INVALID CODE
INVALID CODE
SOFT-SHUTDOWN =
1/8 SLEW RATE SET BY R TIME
INTERNAL
PWM CONTROL
SKIP
FORCED-PWM
FORCED-PWM
PHASEGD
CLKEN
PWRGD
t BLANK
t BLANK
60 μ s TYP
5ms TYP
t BLANK
20 μ s TYP
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
t BLANK
20 μ s TYP
36
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